Arithmetic operations are supported by a variety of central processing units (CPUs), floating point engines (FPEs), and other similar hardware. In some operations, such as floating point addition, it may be appropriate to determine when some portions of an operand assume given bit patterns. For example, it may be useful to determine if a floating point mantissa contains all logical ones, if certain “sticky bits” in an operand are all zeroes, or if operands contain certain predefined patterns of logical values. This processing can be useful, for example, in rounding operations performed in connection with floating point calculations.
To determine when these operands contain the above or other bit patterns, a detector stage can operate on a given input vector. However, some arithmetic operations, such as floating point addition, can involve a plurality of shift operations being performed sequentially on the input vector by successive stages of a multi-stage shifter, with the detector stage following the last one of the shift operations. This scenario results in the entire process being serial in nature, with the output of the detector stage being delayed until after all of the shift operations have been completed by the multi-stage shifter.